Address

Room 101, Institute of Cyber-Systems and Control, Yuquan Campus, Zhejiang University, Hangzhou, Zhejiang, China

Contact Information

Email: gao.muxuan@foxmail.com

Muxuan Gao

PhD Student

Institute of Cyber-Systems and Control, Zhejiang University, China

Biography

I am pursuing my Ph.D. degree in College of Control Science and Engineering, Zhejiang University, Hangzhou, China. My major research interest is robot localization and its computing architecture.

Research and Interests

  • Robot localization and its computing architecture

Publications

  • Muxuan Gao, Juntao Jiang, Shuangming Lei, Huifeng Wu, Jun Chen, and Yong Liu. OnSort: An O(n) Comparison-Free Sorter for Large-Scale Dataset with Parallel Prefetching and Sparse-Aware Mechanism. IEEE Transactions on Circuits and Systems II: Express Briefs, 72:933-937, 2025.
    [BibTeX] [Abstract] [DOI] [PDF]
    This brief proposes OnSort, a parallel comparison free sorting architecture with O(n) time complexity, utilizing the SRAM structure to support large-scale datasets efficiently. The performance of existing comparison-free sorters is limited by uneven value distribution and variable element numbers. To address these issues, we introduce a parallel prefetching strategy to accelerate the indexing process and a sparse-aware mechanism to narrow the indexing search range. Furthermore, OnSort implements streaming execution through a pipelined design, thereby optimizing the previously overlooked latency of the counting phase. Experimental results show that, under the configuration of sorting 65,536 16-bit data elements, OnSort achieves a 1.97× speedup and a 22.6× throughput-to-area ratio compared to the existing design. The source code is available athttps://github.com/gmx-hub/OnSort.
    @article{gao2025onsort,
    title = {OnSort: An O(n) Comparison-Free Sorter for Large-Scale Dataset with Parallel Prefetching and Sparse-Aware Mechanism},
    author = {Muxuan Gao and Juntao Jiang and Shuangming Lei and Huifeng Wu and Jun Chen and Yong Liu},
    year = 2025,
    journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
    volume = 72,
    pages = {933-937},
    doi = {10.1109/TCSII.2025.3570797},
    abstract = {This brief proposes OnSort, a parallel comparison free sorting architecture with O(n) time complexity, utilizing the SRAM structure to support large-scale datasets efficiently. The performance of existing comparison-free sorters is limited by uneven value distribution and variable element numbers. To address these issues, we introduce a parallel prefetching strategy to accelerate the indexing process and a sparse-aware mechanism to narrow the indexing search range. Furthermore, OnSort implements streaming execution through a pipelined design, thereby optimizing the previously overlooked latency of the counting phase. Experimental results show that, under the configuration of sorting 65,536 16-bit data elements, OnSort achieves a 1.97× speedup and a 22.6× throughput-to-area ratio compared to the existing design. The source code is available athttps://github.com/gmx-hub/OnSort.}
    }